ACT88320 datasheet(24/57 Pages) QORVO

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Data Sheet Rev. E, November 2019 | Subject to change without notice

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ACT88320

Advanced PMU with Inrush Control and Bypass Switch

unmasked, it asserts the nIRQ pin. The next level is

when the current increases to the Cycle-by-Cycle

threshold. The buck converter limits the peak switch

current in each switching cycle. This reduces the

effective duty cycle and causes the output voltage to

drop, potentially creating an undervoltage condition.

When the overcurrent condition results in an UV

condition, and UV is not masked, the IC turns off all

supplies for 100ms and restarts. The third level is when

the peak switch current reaches 122% of the Cycle-by-

Cycle current limit threshold. This immediately shuts

down the regulator and waits 14ms before restarting.

For LDOs, the overcurrent thresholds are set by each

LDO’s Output Current Limit setting. When the output

current reaches the Current Limit threshold, the LDO

limits the output current. This reduces the output voltage,

creating an undervoltage condition, causing all supplies

to turn off for 100ms before restarting.

The overcurrent fault limits for the buck converters are

adjustable

via

I2C.

LDO

current

limit

fixed.

Overcurrent fault reporting can be masked via I2C, but

the overcurrent limits are always active and will shut

down the IC when exceeded.

Thermal Warning and Thermal Shutdown

The ACT88320 monitors its internal die temperature

and reports a warning via nIRQ when the temperature

rises above the Thermal Interrupt Threshold of typically

135 deg C. It reports a fault when the temperature rises

above the Thermal Shutdown Temperature of typically

160 deg C. A temperature fault shuts down all outputs

unless the fault is masked. Both the fault and the

warning can be masked via I2C. The temperature

warning and fault flags still provide real-time status even

if the faults are masked. Masking just prevents the faults

from being reported via the nIRQ pin.

INRUSH Control

When power is applied to the system, the OVSNS pin

checks for under voltage and over voltage. If the input

voltage is within spec, the IC turns on an external

N-Channel MOSFET, which supplies power to the VIN

and AVIN pins. VIN and AVIN power the IC, the buck

converters, and the LDOs. The IC controls the voltage

ramp on VIN to control the inrush current from the input

voltage. The gate drive voltage is typically V, which

requires a 12V gate drive FET.

OVP Control

When over voltage is detected on the OVSNS pin, it

generates a fault condition to shutdown the inrush

controller. The overvoltage condition latches VIN output

off until the overvoltage condition is removed. When the

input

voltage

within

specified

limits,

the

automatically restarts. An OVP condition is not reported

via I2C.

Input Current Limit

An external sense resistor can be used between

OVSNS and OVSNS_M to detect the input current to

VIN. An overcurrent warning occurs when the voltage

across the sense resistor reaches 72.5% of the current

limit threshold. The current warning asserts nIRQ low.

The current limit warning can be masked with I2C bit

INRUSH_ILIM_MSK. An overcurrent condition occurs

when the voltage across the sense resistor reaches the

current limit threshold voltage of 85mV. OVGATE

modulates the external MOSFET gate voltage to regu-

late the maximum current through the MOSFET and

protect against an overcurrent condition. If the system

attempts to pull more current, the VIN voltage starts to

drop. If VIN drops below the programmed SYSMON

setting, the IC asserts nIRQ.

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