LM5145 datasheet(58/73 Pages) TI2

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8.4.2 Layout Example

Based on the LM25137F-Q1-EVM5D3 design, Figure 8-26 shows a single-sided layout of a dual-output

synchronous buck regulator. The design uses layer 2 of the PCB as a power-loop ground return path directly

underneath the top layer to create a low-area switching power loop of approximately 2mm². This loop area

must be as small as possible to minimize power-loop parasitic inductance, which results in reduced switch-node

voltage overshoot and ringing (and hence an improved overall EMI signature). See also the LM25137F-Q1-

EVM5D3 Evaluation Module and LM5137F-Q1-EVM12V Evaluation Module EVM user's guides.

Locate the controller close to the power stage –

keep gate drive traces short and direct

Use paralleled 0603

input capacitors close

to the FETs for VIN to

PGND decoupling

Connection to the

EMI filter located

on the bottom side

VOUT2

VIN

SW2

GND

Copper island

connected to AGND pin

Keep the VCC and

BOOT caps close to

their respective pins

Optional jumper to connect VOUT1 and

VOUT2 for a 2-phase implementation

SW1

VOUT1

Figure 8-26. PCB Top Layer

As shown in Figure 8-27, the high-frequency power loop current flows through MOSFETs Q3 and Q4, through

the power ground plane on layer 2, and back to VIN through the 0603 ceramic capacitors C30 through C33. The

currents flowing in opposing directions in the vertical loop configuration provide field self-cancellation, reducing

parasitic loop inductance. Figure 8-28 shows a side view to illustrate the concept of creating a low-profile,

self-canceling loop in a multilayer PCB structure. The layer-2 GND plane layer, shown in Figure 8-27, provides a

tightly-coupled current return path directly under the MOSFETs to the source terminals of Q4.

Four 10nF input capacitors with small 0603 case size, place in parallel close to the drain of each high-side

MOSFET. The low ESL and high self-resonant frequency (SRF) of the small footprint capacitors yield excellent

high-frequency performance. The negative terminals of these capacitors connect to the layer-2 GND plane with

multiple 12mil (0.3mm) diameter vias, further reducing parasitic inductance.

Additional steps used in this layout example include:

• Keep the SW connection from the power MOSFETs to the inductor (for each channel) at minimum copper

area to reduce capacitive coupling and radiated EMI.

• Locate the IC close to the power MOSFETs and keep the gate drive traces short and direct. Route the HO

and SW traces as a diff pair and run the LO trace above or below a ground plane.

LM25137

SNVSCU4 – OCTOBER 2025

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