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TPSM84A21

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SLVSDF7A – DECEMBER 2016 – REVISED JULY 2017

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8.2.2 Detailed Design Procedure

8.2.2.1 Setting the Output Voltage

The output voltage of the TPSM84A21 is externally adjustable using a single resistor (RSET). Select the value of

RSET from or calculate using Equation 5:

(5)

To set the output voltage to 1.0 V, the calculated value for RSET is 1.03 kΩ. The closest E96 value is 1.02 kΩ.

8.2.2.2 Input and Output Capacitance

The TPS84A21 requires no external input or output capacitance to operate. Input and output capacitors can be

added to improve ripple or transient response. In this design example, in order to meet the ±2% voltage deviation

for a 5-A, 5-A/µs load step, 100 µF of output capacitance is required.

8.2.2.3 Power Good (PGOOD)

Applications requiring voltage rail sequencing can benefit from the PGOOD signal present with the TPSM84A21.

The PGOOD pin is an open drain output. When the output voltage is typically between 95% and 105% of the set

point, the PGOOD pin pull-down is released and the pin floats, requiring an external pull-up resistor for a high

signal. A 10-kΩ pull-up resistor is placed between the PGOOD pin and an external 5V rail.

8.2.2.4 External VG Voltage

The VG supply rail is used to power the internal gate drivers and other internal supply rails used by the

controller. For best efficiency, supply an external 5 V to the VG pin, thereby overriding the internal 4.8 V

regulator. Expect a 2-3% efficiency improvement by driving the VG pin with an external 5V.

8.2.3 Application Curves

VIN = 12 V

VOUT = 1.0 V

Figure 18. Start-up Waveforms

VIN = 12 V

VOUT = 1.0 V

Load Step = 5 A

COUT = 100 µF

Slew Rate = 1 A/µs

Figure 19. Application Transient Response