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TPSM84A21

SLVSDF7A – DECEMBER 2016 – REVISED JULY 2017

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Layout Examples (continued)

Figure 22 shows a layout with the placement of additional ceramic input capacitors (C1, C3) and ceramic output

capacitors (C2, C4) for designs that require additional ripple reduction or improved transient response. Figure 23

shows a typical internal PCB layer with a trace connecting the VS+ pin to VOUT near the load

Figure 22. Layout with Optional CIN and COUT

Figure 23. VS+ Trace on Internal Layer