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TPSM84A21

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SLVSDF7A – DECEMBER 2016 – REVISED JULY 2017

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Copyright © 2016–2017, Texas Instruments Incorporated

10 Layout

10.1 Layout Guidelines

To achieve optimal electrical and thermal performance, an optimized PCB layout is required. Figure 20 and

Figure 22 show typical, top-side PCB layouts. Some considerations for an optimized layout are:

•

Use large copper areas for power planes (VIN, VOUT, and PGND) to minimize conduction loss and thermal

stress.

•

When adding input and output ceramic capacitors, place them close to the device pins to minimize high

frequency noise.

•

Locate any additional output capacitors between the ceramic capacitors and the load.

•

Keep AGND and PGND separate from one another. The connection is made internal to the device.

•

Place RSET as close as possible to the VADJ pin.

•

Use multiple vias to connect the power planes to internal layers.

10.2 Layout Examples

The layout shown in Figure 20 shows the minimum solution size with only a single voltage setting resistor (R1)

as the only additional required component. Figure 21 shows a typical internal PCB layer with a trace connecting

the VS+ pin to VOUT near the load.

Figure 20. Minimum Component Layout

Figure 21. VS+ Trace on Internal Layer