EN/

UVLO

PGND

VIN

Q1

EN

Control

14

TPSM84A21

SLVSDF7A – DECEMBER 2016 – REVISED JULY 2017

www.ti.com

Product Folder Links: TPSM84A21

Submit Documentation Feedback

Copyright © 2016–2017, Texas Instruments Incorporated

7.3.10 Thermal Shutdown

The internal thermal shutdown fault is triggered if the junction temperature exceeds 135°C (typ). This interrupts

regulation by making the output high impedance. The device reinitiates the power up sequence when the junction

temperature drops below 115°C (typ).

7.3.11 Overcurrent Protection

For protection against load faults, the TPSM84A21 incorporates output overcurrent protection. Applying a load

that exceeds the module's overcurrent threshold causes the output to shut down and PGOOD is pulled low.

Following shut down, the module attempts to restart after a 32.8-ms hiccup interval counter has expired. This

provides a hiccup response to an overcurrent condition. During this period, the average current flowing into the

fault is significantly reduced which reduces power dissipation. Once the fault is removed, the module

automatically recovers and returns to normal operation.

The TPSM84A21 overcurrent trip point is 15 A (typ) when the ILIM pin is left open. This provides enough margin

for brief overshoots in inductor currents during a load transient while at the same time protecting against short

circuits or other potentially catastrophic faults on the output. The overcurrent trip point can be reduced to

11.25 A (typ) by placing a 47 kΩ between the ILIM pin and PGND. Programming resistors with up to ±5%

variation can be used. The current limit selection is latched in at power up and cannot be changed without

cycling input power or the EN pin voltage.

7.3.12 Output Undervoltage/Overvoltage Protection

The device incorporates an output undervoltage/overvoltage protection (UVP/OVP) circuit to prevent damage to

the load. This fault can be triggered during large, fast load transients if insufficient output capacitance is used.

The UVP/OVP feature compares the VADJ pin voltage to internal thresholds. If the VADJ pin voltage is lower

than 90% or greater than 110% of the nominal internal reference voltage, the module is turned off, a fault is

triggered, and the PGOOD pin is pulled low. When the fault hiccup interval is complete, the module will attempt

to restart.

7.3.13 Enable (EN)

The EN pin provides electrical on and off control of the TPSM84A21. Once the EN pin voltage exceeds the

threshold voltage, the device starts operation. If the EN pin voltage is pulled below the threshold voltage, the

module stops switching and enters a low power state. There is no voltage hysteresis in the EN threshold. The

rising and falling voltage thresholds occur at the same level. The EN pin has an internal pull-up current source,

allowing the user to float the EN pin for enabling the device.

If an application requires controlling the EN pin, use an open drain/collector device or a suitable logic gate to

interface with the pin. Figure 15 shows controlling the EN/UVLO pin using a MOSFET, Q1. Turning Q1 on,

disables the device. Using a voltage superviser to control the EN pin allows control of the turn-on and turn-off of

the device as opposed to relying on the ramp up or down of the input voltage source.

Figure 15. Enable Control