VIN

PGND

VOUT

VADJ

VS+

TPSM84A21

1 kO

VREF

Power

Stage

and

Control

Logic

VIN

UVLO

Oscillator

SYNC

Soft

Start

PGOOD

Protection

and

Supervisory

Circuits

ILIM

EN/UVLO

VG

REG

4 MHz

10 O

VOUT

Error

Amp

AGND

Copyright © 2016, Texas Instruments Incorporated

10

TPSM84A21

SLVSDF7A – DECEMBER 2016 – REVISED JULY 2017

www.ti.com

Product Folder Links: TPSM84A21

Submit Documentation Feedback

Copyright © 2016–2017, Texas Instruments Incorporated

7 Detailed Description

7.1 Overview

The TPSM84A21 is a 14-V, 10-A, synchronous series capacitor step-down (buck) power module. The

TPSM84A21 combines a 10-A DC/DC converter with power MOSFETs, shielded inductors, series capacitor,

input and output capacitors, and passives into a low profile, overmolded package. The integrated input and

output capacitors allows standard applications to operate with no additional input or output capacitors and only a

single resistor to set the output voltage.

The integrated components allow for high-efficiency, high-density, complete power supply designs with

continuous output currents up to 10 A. The TPSM84A21 reduces the external component count by integrating

both the input and output capacitors. The TPSM84A21 input voltage range is 8 V to 14 V with an output voltage

range of 0.508 V to 1.35 V.

The TPSM84A21 is a two-phase power supply with each phase switching at a fixed 2 MHz frequency, resulting

in the internal oscillator frequency of 4 MHz. An external synchronization clock can also be provided via the

SYNC pin.

The TPSM84A21 starts up safely into loads with pre-biased outputs (non-zero volts at startup). The device

implements an internal input voltage under voltage lockout (UVLO) feature which can be adjusted higher by

adding an external resistor divider on the EN/UVLO pin. Electrical ON/OFF control is provided using the enable

(EN) feature. The TPSM84A21 is disabled by pulling the EN pin low. When the device is disabled, the supply

current is typically less than 50 μA.

The TPSM84A21 has a power good comparator (PGOOD) which monitors the output voltage through the VS+

pin. The PGOOD pin is an open-drain MOSFET which is held low until the output voltage is within ±5% of the set

voltage. The PGOOD pin is held low during startup or when a fault occurs.

7.2 Functional Block Diagram