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TPSM84A21

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SLVSDF7A – DECEMBER 2016 – REVISED JULY 2017

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Copyright © 2016–2017, Texas Instruments Incorporated

7.3.4 Oscillator Frequency

The oscillator frequency of this converter is set at 4 MHz. The per phase switching frequency of the converter is

half the oscillator frequency, or 2 MHz per phase. The oscillator frequency is fixed internally.

During load transients, the internal control loop will momentarily change the switching frequency in order to meet

the output voltage recovery.

7.3.5 External Clock Syncronization

An external clock can be connected to the SYNC pin. The external clock signal overrides the internal oscillator

and is used as the system clock. This feature enables the user to synchronize the switching events to a master

clock on their board. The internal phase locked loop (PLL) has been implemented to allow synchronization at

frequencies between ±10% of the nominal oscillator frequency. This allows the user to easily switch between the

internal oscillator mode and the external clock mode while converting power. Before the external clock is present

or after it is removed, the device with default to the internal oscillator setting.

To implement the synchronization feature, connect a square wave clock signal to the SYNC pin with a duty cycle

between 20% and 80%. The clock signal amplitude must transition lower than 0.8 V and higher than 2 V. The

start of the switching cycle is synchronized to the rising edge of the SYNC pin. The device can be configured for

operation in applications where both an internal oscillator mode and an external synchronization clock mode are

needed. Before the external clock is present, the switching frequency of the device is set by the internal

oscillator. When the external clock is present, the SYNC mode overrides the internal oscillator. The first time the

SYNC pin is pulled above the SYNC high threshold (2 V), the device switches from the internal oscillator mode to

the SYNC mode and the PLL starts to lock onto the frequency of the external clock. When the external SYNC

clock is removed, the converter will transition back to the internal oscillator after 4 internal clock cycles.

7.3.6 Soft Start

The TPSM84A21 has a pre-programmed soft start time of 4.1 ms (typ). The soft start time is the time it takes for

the output voltage to rise from zero volts to the voltage set by the RSET resistor. Soft start is an important feature

that limits inrush current and reduces the load on the input supply to this device. During soft start, the internal

reference voltage is slowly ramped up to the internal reference voltage. This slowly increases the commanded

output voltage of the converter and reduces the initial surge in current. During soft start PGOOD remains low, the

PLL is not active, and output UVP/OVP faults are disabled.

7.3.7 Power Good (PGOOD)

The Power Good (PGOOD) pin is an open drain output. After startup, when the VADJ pin is typically between

95% and 105% of the internal voltage reference, the PGOOD pin pull-down is released and the pin floats. The

recommended pull-up resistor value is between 10 kΩ and 100 kΩ to a voltage source of 5.5 V or less. For

convenience, VG can be used as the pull-up voltage. The PGOOD is in a defined state once the VIN input

voltage is greater than approximately 1.2 V, but with reduced current sinking capability. The PGOOD achieves

full current sinking capability once the VIN input voltage is above the input UVLO. The PGOOD pin is pulled low

when the VADJ pin voltage is typically lower than 95% or greater than 105% of the nominal internal reference

voltage. The PGOOD pin is also pulled low if a fault is detected, the EN pin is pulled low, or the converter is

performing its soft-start power up sequence.

7.3.8 Gate Driver (VG)

A linear regulator internal to the TPSM84A21 generates a 4.8 V internal supply rail on the VG pin. The input of

the linear regulator comes from the VIN pin. The VG supply rail is used to power the internal gate drivers and is

the input to another regulator that generates the internal supply rails used by the controller. To improve converter

efficiency, an external 5 V supply is recommended to be connected to the VG pin, thereby overriding the internal

4.8 V regulator. This external supply must be between 5.0 V and 5.5 V and must be present before applying

input voltage to the VIN pin. If not supplying an external voltage to this pin, leave this pin open.

7.3.9 Startup into Pre-biased Outputs

The TPSM84A21 prevents the low-side MOSFETs from discharging a pre-biased output. During pre-biased

startup, the low-side MOSFETs do not turn on until after the high-side MOSFETs have started switching. The

high-side MOSFETs do not start switching until the internal soft-start reference voltage exceeds the voltage at

the VADJ pin.