AD5710R datasheet(32/56 Pages) AD

32 / 56 page

Data Sheet

AD5710R

DIGITAL INTERFACE

analog.com

Rev. 0 | 32 of 56

When multiple AD5710R are connected to the same SPI bus,

especially on the SDO line, the capacitive load increases due to

the input capacitance of each device connected on the bus and the

PCB trace capacitance. This increased capacitance slows down the

signal transitions (rise and fall times), which can cause the data on

the SDO line to not settle in time before the host samples it on the

next clock edge. It is, therefore, recommended to reduce the SCLK

frequency to allow more time for the SDO to settle after a transition.

DEVICE STATUS ERRORS

The AD5710R has a INTERFACE_STATUS_A register that con-

tains all the status bits related to the digital interface. These status

bits are set based on the actions related to the SPI transactions,

until explicitly clearly by writing a 1 to the bit location to clear the

status bit.

Partial Register Access Error

The REGISTER_ PARTIAL_ACCESS_ERR bit in the INTER-

FACE_STATUS_A register is set when a multibyte register is

accessed for read or write partially, which means that the transac-

tion ends before all the bytes of a multibyte register have been

accessed. To clear this error, write 1 to the REGISTER_ PARTI-

AL_ACCESS_ERR bit.

Invalid/No CRC Received Error

The CRC_ERR bit in the INTERFACE_STATUS_A register is set

when the CRC is enabled and the CRC byte in the SPI transaction

is missing or does not match the calculated value. To clear this

error, write 1 to this bit. Note that because the CRC is enabled, this

SPI transaction must have a valid CRC code to succeed.

Clock Counting Error

The error reported in the CLOCK_COUNT_ERR bit is produced

when the number of SCLK cycles is not in accordance with the

amount required to shift a multiple of eight bits.

Interface Not Ready Status

The NOT_READY_ERR bit in the INTERFACE_STATUS_A register

is not an error. It is a status bit that can be polled to know when the

device is ready to receive data from the host. This bit is a read or

write one to clear (R/W1C) type of bit and can be cleared by writing

1 to it.

CYCLIC REDUNDANCY CHECK (CRC) ERROR

DETECTION

The AD5710R DAC features an optional cyclic redundancy check

(CRC) to provide error detection for SPI transactions between the

digital host and the DAC (target). The CRC error detection is

disabled by default. CRC error detection allows the SPI host and

targets to detect bit transfer errors with significant reliability. The

CRC algorithm involves using a seed value and polynomial division

to generate a CRC code. The controller and target both calculate

the CRC code independently to determine the validity of transferred

data.

This DAC uses the CRC-8 standard with the following polynomial:

x8+x2+x+1

(9)

CRC error detection is enabled with the CRC_EN and CRC_EN_B

bits in the INTERFACE_CONFIG_C register. The value of CRC_EN

is only updated if CRC_EN_B is set to the CRC_EN inverted value

in the same register write instruction. Therefore, to enable the CRC,

the CRC_EN must be set to 0b01 while CRC_EN_B is set to 0b10

in the same write transaction.

To disable the CRC, the CRC_EN must be set to 0b00 and the

CRC_EN_B is set to 0b11 in the same write transaction.

Writing inverted values to two separate fields reduces the chances

of CRC being enabled in error. The CS must be brought high at

the end of the enable/disable write. The first CRC code must be

included after the register write/read data, immediately following

the register write transaction enabling the CRC. A register write

transaction that disables the CRC must still include the CRC code

on SDI, but the following transaction does not require the CRC

code.

Figure 71 and Figure 72 show how a CRC code is appended to the

write or read, respectively, for the digital host or DAC to validate

the data. For register writes, the digital host must generate the CRC

using the calculation described in Equation 9. For register reads,

the host must also send the correct CRC byte that is checked

by the DAC. The first byte of data sent contributes to the CRC

calculation. Therefore, a value of 0x00 is recommended. In the

same read transaction, the DAC provides the CRC code for the

digital host to verify.

When accessing multibyte registers with the CRC error detection

enabled, the CRC code is placed after all bytes of register data.

Figure 71. SPI Write with CRC Enabled

Figure 72. SPI Read with CRC Enabled

When the CRC error detection is enabled, the DAC does not up-

date its register contents in response to a register write transaction

unless it receives a valid CRC code at the end of the register data

on the SDI. If the CRC code is invalid, or the digital host fails to

transmit the CRC code, the AD5710R does not update its register

AD5710R Datasheet(PDF) 32 Page - Analog Devices

AD5710R Datasheet(HTML) 32 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56

Datasheet Download

Link URL