Data Sheet

AD5710R

ELECTRICAL CHARACTERISTICS

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Rev. 0 | 3 of 56

DC SPECIFICATIONS

AVDD = 2.7V to 5.5V, PVDDx = 2.7V to AVDD for VDAC channels, PVDDx = 1.71V to AVDD for IDAC channels, IOVDD = 1.08V to 1.98V,

VREF = 2.5V (internal or external), all specifications are at TJ = −40°C to +125°C. Typical specifications at TA = 25°C, unless otherwise noted.

RL = 2kΩ, CL = 200pF for VDAC channels. RL = 50Ω for IDAC channels. No capacitor on VREF.

Table 1. DC Specifications

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

VDAC STATIC PERFORMANCE

Resolution

16

Bits

Integral Nonlinearity (INL)1

−10

+10

LSB16

Differential Nonlinearity (DNL)1

−1

+1

LSB16

Guaranteed monotonic

Zero-Code Error

−4.6

1.5

+4.6

mV

Offset Error2

−5.2

1.4

+5.2

mV

Gain Error

−0.3

0.02

+0.3

% of FSR

Range = 0 to VREF

0.04

% of FSR

Range = 0 to 2 × VREF

Total Unadjusted Error (TUE)

−0.34

±0.08

+0.34

% of FSR

Range = 0 to VREF

−0.16

±0.04

0.16

% of FSR

Range = 0 to 2 × VREF

Offset Error Drift

1.5

µV/°C

Range = 0 to VREF

2.5

µV/°C

Range = 0 to 2 × VREF

Gain Error Drift

18

ppm/°C

Range = 0 to VREF

25

ppm/°C

Range = 0 to 2 × VREF

DC Power Supply Rejection Ratio

(PSRR)

AVDD

33

μV/V

DAC code = midscale, AVDD = 5V ± 10%

PVDD

16

μV/V

DAC code = midscale, PVDD = 5V ± 10%

DC Crosstalk

VDAC to VDAC

4.5

µV

Due to single channel, full-scale output change, internal

reference, and range = 0 to VREF

35

µV/mA

Due to single channel, from −10mA to +10mA load current

change, internal reference, and range = 0 to VREF

14

µV

Due to powering down (per channel), internal reference, and

range = 0 to VREF

IDAC to VDAC

168

µV

Due to single channel, full-scale output change, internal

reference, and range = 0 to VREF

298

µV

Due to powering down (per channel), internal reference, and

range = 0 to VREF

VDAC OUTPUT CHARACTERISTICS

Output Voltage Range

0

VREF

V

Range = 0 to VREF

0

2 × VREF

V

Range = 0 to 2 × VREF

Short Circuit Current

50

mA

Sourcing

10

mA

Sinking

Capacitive Load Stability

2

nF

RL = ∞

10

nF

RL ≤ 2kΩ

Load Regulation

200

µV/mA

PVDD = 5V ± 10%, DAC code = midscale, −30mA ≤ IOUT ≤

+30mA

200

µV/mA

PVDD = 3V ± 10%, DAC code = midscale, −20mA ≤ IOUT ≤

+20mA

Headroom

70

50

mV

Source current = 20mA

Footroom

250

120

mV

Sink current = 10mA

Output Impedance

10

Ω

Output close to VDD or GND

Power-Up Time

4.5

µs

Exiting power-down mode, AVDD = PVDD = 5V