AD5710R datasheet(26/56 Pages) AD

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Data Sheet

AD5710R

DAC CORE FUNCTIONS

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Rev. 0 | 26 of 56

Option 1 (Immediate Update, Unique Data, No

LDAC, and Single and Multiple Channels)

Option 1 allows the immediate update of DAC_CHn registers after

writing the whole 16-bit data. An LDAC is not required, and it is

applicable to both single channel and multiple channel updates in

single instruction or stream modes.

A single instruction is sent with the descending mode selected. The

higher address of the multibyte register is called on the instruction

phase (0xD3 : DAC_CH0 register, followed by two 8-bit data) that

updates the output immediately after the last SCLK.

Figure 57. Option 1 Example: Write to the DAC_Ch0 Register, Single

Instruction Mode, and Address Descending

Option 2 (Controlled Update, Unique Data,

Hardware LDAC, and Single and Multiple

Channels)

Option 2 allows controlled update timing of the DAC_CHn registers

from the INPUT_CHn registers through a hardware LDAC.

This option is applicable to both single channel and multiple chan-

nel updates in single instruction or stream modes.

A single instruction is sent to write to the HW_LDAC_EN_0 register,

enabling a hardware LDAC for the selected channels. Then a

stream mode is initiated, in default descending mode, writing to the

INPUT_CH7 first up to INPUT_CH0. The LDAC is asserted at the

end of the stream updating the DAC registers and the DAC output

(if the correct LDAC timing is observed).

Figure 58. Option 2 Example: Write to the INPUT_CH7 to INPUT_CH0

Registers, Hardware LDAC Enabled, Stream Mode, and Address Descending

Option 3 (Controlled Update, Unique Data,

Software LDAC, and Single and Multiple

Channels)

Option 3 allows controlled update timing of the DAC_CHn registers

from the INPUT_CHn registers through the software LDAC.

This option is applicable to both single channel and multiple chan-

nel updates in single instruction and stream modes.

This option is similar to Option 2, except a software LDAC func-

tion is used instead of a hardware LDAC. The SW_LDAC_EN_0

LDAC command. The DAC registers and DAC outputs are updated

with the input data written after the last SCLK of the SW LDAC

command.

Figure 59. Option 3 Example: Write to the INPUT_CH7 and INPUT_CH6

Registers with a Software LDAC, Stream Mode, and Address Descending

Option 4 (Immediate Update, Same Data, No

LDAC, and Multiple Channels)

Option 4 allows the immediate and simultaneous update of

multiple DAC_CHn registers identified by MULTI_DAC_SEL_0

(MD_SEL_CH_n) bitfields with the same data. Data is contained

in MULTI_DAC_CH register and the update is initiated after writing

the whole 16-bit data. An LDAC is not required.

Option 4 is ideal for multiple channel updates in both single instruc-

tion and stream modes.

A write instruction is sent to the MULTI_DAC_SEL_0 register, ena-

bling multiple DAC functions for the selected channels. With stream

mode descending enabled, the next commands are the data for

the adjacent multibyte register 0xE3 (and 0xE2) MULTI_DAC_CH.

Assuming that STREAM_MODE(LOOP_COUNT) is set to 0x3, the

succeeding data stream loops back to the start address, 0xE4, and

repeats the process, until CS is deasserted.

Figure 60. Option 4 Example: Write to the MULTI_DAC_CHn Register, Stream

Mode (Loop), and Address Descending

Option 5 (Controlled Update, Same Data,

Hardware LDAC, and Multiple Channels)

Option 5 allows for the controlled update tim-

ing of multiple DAC_CHn registers identified

by the MULTI_INPUT_SEL_0(MI_SEL_CH_n) and

HW_LDAC_EN_0(HLD_EN_CH_n) bitfields with the same data.

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