AD5710R datasheet(27/56 Pages) AD

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Data Sheet

AD5710R

DAC CORE FUNCTIONS

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Rev. 0 | 27 of 56

Data is contained in the MULTI_INPUT_CHn register, and the

update is initiated by providing a valid LDAC pulse.

Option 5 is ideal for multiple channel updates in both single instruc-

tion and stream modes. This option is similar to Option 2, except

Option 5 makes use of the MULTI_INPUT_SEL_0 and MULTI_IN-

PUT_CHn registers to select and update the input registers of

multiple DAC channels. The LDAC is asserted after each loop

ends, updating the DAC registers and the DAC outputs (when

correct LDAC is observed).

Figure 61. Option 5 Example: Write to MULTI_INPUT_CHn Register with a

Hardware LDAC, Stream Mode (Loop), and Address Ascending

Option 6 (Controlled Update, Same Data,

Software LDAC, and Multiple Channels)

Option 6 allows immediate and simultaneous

updating of multiple DAC_CHn registers identi-

fied by the MULTI_INPUT_SEL_0(MI_SEL_CH_n) and

SW_LDAC_EN_0(SLD_EN_CH_n) bitfields with the same data.

Data is contained in MULTI_INPUT_CHn register and is initiated

through the software LDAC.

Option 6 is ideal for multiple channel updates in both single

instruction and stream modes. It is similar to Option 5, except a

software LDAC function is used instead of a hardware LDAC. The

SW_LDAC_EN_0 register determines which channel is affected by

a software LDAC command.

Figure 62. Option 6 Example: Write to MULTI_INPUT_CHn Register with a

Software LDAC, Stream Mode (Loop), and Address Ascending

AD5710R Datasheet(PDF) 27 Page - Analog Devices