AD5710R datasheet(29/56 Pages) AD

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Data Sheet

AD5710R

DIGITAL INTERFACE

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Rev. 0 | 29 of 56

Figure 65. Multibyte Read in Ascending Mode

Figure 66. Multibyte Read in Descending Mode

Address direction is selected with the INTERFACE_CONFIG_A, Bit

5 (ADDR_ASCENSION). If this bit is set to 0, the address decre-

ments after each byte is accessed. If this bit is set to 1, the address

increments after each byte is accessed. If a SPI write transaction

to a multibyte register is attempted on a per byte basis, the register

contents are not updated on the device, and the INTERFACE_STA-

TUS_A, Bit 1 (REGISTER_PARTIAL_ACCESS_ERR) is set.

This device contains the following multibyte registers: DAC_CHn,

INPUT_CHn, MULTI_DAC_CH, and MULTI_INPUT_CH.

SINGLE INSTRUCTION MODE

When the INTERFACE_CONFIG_B, Bit 7 (SINGLE_INST) is set

to 1, streaming mode is disabled, and single instruction mode is

enabled. In single instruction mode, the data phase consists of data

for a single register, and each data phase must be followed by a

new instruction phase (even if CS remains low). Single instruction

mode allows the digital host to quickly read from and write to

registers with nonadjacent addresses in a single SPI frame (see

Figure 67), whereas streaming mode only allows either reading or

writing to contiguous registers without pulsing CS high to initiate a

new instruction phase.

When accessing multibyte registers in single instruction mode, data

phase should include all two bytes or 16 SCLK cycles, and the reg-

ister address order is dependent on the INTERFACE_CONFIG_A,

Bit 5 (ADDR_ASCENSION).

Figure 67. Single Instruction Mode

AD5710R Datasheet(PDF) 29 Page - Analog Devices