AD5710R datasheet(24/56 Pages) AD

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Data Sheet

AD5710R

DAC CORE FUNCTIONS

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Rev. 0 | 24 of 56

Each DAC channel has an individual input register and a DAC

through the serial interface. The DAC register stores digital code

equivalent to the DAC output voltage while the input register acts

as a temporary staging register before being passed on to the DAC

updated in parallel with the data held in the input registers.

The DAC registers can be written to directly, in which case the

corresponding output updates immediately without the need for a

hardware or software LDAC. Directly writing to the DAC register

does not affect the data stored in the input register.

Writing to the MULTI_INPUT_CH register allows one or more input

registers to be updated in a single write operation. The MULTI_IN-

PUT_SEL_0 register determines which channel's input register can

be updated with the data written to the MULTI_INPUT_CH register.

See the DAC Update section for additional information.

Similarly, writing to the MULTI_DAC_CH register allows one or

more DAC registers to be updated in a single write operation.

MULTI_DAC_INPUT_SEL_0 determines which DAC register can be

updated with the data written to the MULTI_DAC_CH register. See

the DAC Update section for more information.

To ensure that the DAC update is successful, DAC register updates

should only occur once every 640ns. Refer to tL2 and tL3 from

Table 3. An error flag is asserted when a DAC update write is

unsuccessful, which can be check by reading the UPDATE_ERR bit

on the STATUS_CONTROL_0 register.

LDAC FUNCTION

The LDAC function is used to initiate the transfer of the contents

of input registers of the selected channels to the corresponding

DAC registers, thereby updating one or more OUT pins at the same

time. The LDAC function can be executed by hardware through

the LDAC pin or by software through SW_LDAC_TRIG_A or

SW_LDAC_TRIG_B registers. Both hardware and software LDAC

perform the same function.

Hardware LDAC

The AD5710R has an active low LDAC pin that is falling edge

sensitive. If the LDAC signal is brought low, the selected input

the LDAC is held low when writing to the device, the input registers

appear transparent, and when an input register is written to, the

DAC register is updated with the contents of the input register at the

same time. When LDAC is held high, DAC codes can be written to

any input registers without affecting the DAC output.

The LDAC is used to determine the DAC channels to be updated

from the input registers of the corresponding DAC channels when

LDAC is active low or asserted. By default, all DAC channels are

selected and the HLD_EN_CH_n bitfields contain a 1b'1. A 1b'0 set

on a HLD_EN_CH_n bitfield disables the hardware LDAC feature

for the corresponding DAC channel.

Software LDAC

The software LDAC function is synonymous to an LDAC falling

edge. It provides a way to initiate a transfer of content between

input registers of the selected DAC channels to corresponding

DAC registers through the serial interface via writing 1b'1 to

SLD_TRIG_A bit on the SW_LDAC_TRIG_A register or to the

SLD_TRIG_B bit on the SW_LDAC_TRIG_B register.

The SW_LDAC_EN_0 register is used to determine the DAC chan-

nels to be updated from the corresponding input registers when

a software LDAC is performed. By default, all DAC channels are

selected and the SLD_EN_CH_n bitfields contain a 1b'1. A 1b'0 set

in a SLD_EN_CH_n bitfield disables the software LDAC feature for

the corresponding DAC channel.

DAC UPDATE

There are multiple methods for updating the DAC_CHn registers

that directly affect the VDAC and IDAC outputs. Figure 55 applies

when unique data is written to one or more channels, with varia-

tions depending on whether the update is immediate or controlled

using the hardware or software LDAC. Figure 56 applies when the

same data is written to multiple channels, allowing for immediate

or simultaneous updates or controlled updates using either the

hardware or software LDAC. The appropriate method depends on

whether a single channel or multiple channels are being updated,

whether the data is unique or the same, and the configuration of the

LDAC signal.

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