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Data Sheet

AD5710R

THEORY OF OPERATION

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DIGITAL-TO-ANALOG CONVERTER

The AD5710R is a low power, 8-channel, 16-bit DAC that operates

on analog supply voltages of 2.7V to 5.5V for AVDD, 1.71V to

AVDD for PVDD0/1 and interface logic supply IOVDD of 1.08V

to 1.98V. Each channel can be configured as VDAC or IDAC. A

group of four DAC channels, OUT[3:0], is powered by PVDD0 and

another group of four DAC channels, OUT[7:4], is powered by

PVDD1.

The device has a 3ppm/°C, 2.5V on-chip reference and incorpo-

rates various functions such as load DAC, device reset, output

monitoring, and die temperature monitoring. A simplified block

diagram of a DAC channel is shown in Figure 53.

The AD5710R offers a versatile 4-wire serial interface compatible

with classic SPI. See the Digital Interface section for more details.

Figure 53. DAC Channel Block Diagram

IDAC Channels

The device integrates eight 16-bit current-output DAC (IDAC) chan-

nels. Each channel is configured as an IDAC by default and is

capable of sourcing currents up to 50mA.

The input coding to the DAC is straight binary. The conversion of

the digital input code to the ideal output voltage is given by the

following equation:

IOUTn= D2N ×50 mA

(2)

where:

IOUTn is the output current sourced through the load at the selected

DAC channel n.

D is the decimal equivalent of the straight binary code that is loaded

into the DAC register.

N is the DAC resolution in bits.

By default, the output of any channel is configured as IDAC in high-

Z mode and the output stage of each channel is powered down.

Alternatively, each channel can be configured as IDAC output by

setting the corresponding CHx_VMODE_EN bit to 0. The output of

each channel can be enabled by writing 2'b00 to MODE_CH_x bits

corresponding to each channel.

VDAC Channels

The device contains eight buffered VDAC channels capable of

sourcing 50mA and sinking 10mA current independently. VDAC

channels have a shared gain bit OUTPUT_CONTROL_0, that sets

the output range to 0V to VREF or 0V to 2 × VREF. Consequently, it

is not possible to set different output ranges on a per channel basis.

The input coding to the DAC is straight binary. The conversion of

the digital input code to the ideal output voltage is given by the

following equation:

VOUTn=VREF× D2N ×G

(3)

where:

VOUTn is the output voltage seen at the selected DAC channel n.

VREF is the voltage present on the VREF pin. For internal reference,

VREF= 2.5V.

D is the decimal equivalent of the straight binary code that is loaded

into the DAC register.

N is the DAC resolution in bits.

G is the gain of the output amplifier. G = 1 if OUTPUT_CON-

TROL_0, Bit 2 (range) = 0 (default), and G = 2 if OUTPUT_CON-

TROL_0, Bit 2 (range) = 1.

By default, the output of any channel is configured as IDAC in

high-Z mode. Each channel can be configured as VDAC output

by setting the corresponding CHx_VMODE_EN bit to 1. The DAC

output has an effective output resistance of 15kΩ to GND during

the shutdown state. The output of each channel can be enabled by

writing 2'b00 to MODE_CH_x bits corresponding to each channel.

Output Voltage Limitation Due to PVDD

When PVDD is configured below the selected VDAC output range,

the output voltage of the channel is limited and clamps just below

PVDD, regardless of the applied full-scale digital code. In such

conditions, the device cannot achieve the full-scale output voltage

of 2.5V for an output range of VREF or 5V for an output range of 2

× VREF.

DAC Operating Modes

Upon power-up or following a power-on reset, all channel outputs

default to a high-impedance (high-Z) state while operating in IDAC

mode. In this state, the output stage of each channel is powered

down. To enable output, the corresponding channel must be config-

ured by writing 2'b00 to the MODE_CH_x bits.

By default, each channel is configured as an IDAC. To switch

a channel to VDAC mode, set the VMODE_EN_CHn bit for the

respective channel. Prior to transitioning between IDAC and VDAC

modes, the DAC register for the corresponding channel must be

cleared to 0x0000.

Note that in power-down mode, VDAC channels exhibit an effective

internal output resistance of approximately 15 kΩ to GND.

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