AD5710R datasheet(28/56 Pages) AD

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Data Sheet

AD5710R

DIGITAL INTERFACE

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Rev. 0 | 28 of 56

The device uses a 4-wire serial interface (CS, SCLK, SDI, and

SDO) that is compatible with classic SPI, QSPI, and MICROWIRE

interface standards, as well as most digital signal processors

(DSPs).

See Figure 2 for a timing diagram of a typical read-write sequence.

high, SCLK edges are ignored, and SDO is high-Z. A falling edge

on CS initiates a SPI frame. For all SPI transactions, data is shifted

MSB first.

Data is sampled by the device on the rising edge of the SCLK while

the data is shifted out on SDO on the falling edges of SCLK. This

corresponds to SPI Mode 0 (CPOL = 0, CPHA = 0).

Communication with the device is separated into two distinct phas-

es of operation. The first phase is the instruction phase and is

used to initiate some action of the device. In the instruction phase,

the register address is 15-bit wide (SHORT_INSTRUCTION bit =

0 in the INTERFACE_CONFIG_B register) by default. The second

phase is the data phase where the data is either passed to the

device to operate on or received from the device in response to the

instruction phase.

Figure 63 shows a SPI write transaction using a 15-bit address in

the instruction phase and eight bits for a single byte register for the

data phase while Figure 64 shows a SPI read transaction using a

7-bit address in the instruction phase and eight bits for the data

phase.

Figure 63. Classic SPI Write

Figure 64. Classic SPI Read

SPI FRAME SYNCHRONIZATION

The CS pin frames data during a SPI transaction. A falling edge on

the CS enables the digital interface and initiates a SPI transaction.

Each SPI transaction consists of at least one instruction phase

and one data phase. For all SPI transactions, data is aligned MSB

first. Deasserting the CS during a SPI transaction terminates part

or all of the data transfer and disables the digital interface. If the

CS is deasserted (returned high) after one or more registers are

written, completed registers are written or read, but any partially

written register is aborted. Figure 63 and Figure 64 show detailed

timing diagrams for performing register reads and writes via the SPI

interface.

INSTRUCTION PHASE

Every SPI frame starts with the instruction phase. The instruction

phase immediately follows the falling edge of the CS that initiates

the SPI transaction. The instruction phase consists of a read/write

bit (R/W) followed by a register address word. Setting R/W low

initiates a write instruction, whereas setting R/W high initiates a

read instruction. The register address word specifies the address

of the register to be accessed. The register address word is 15

bits in length by default. If required, enable 7-bit addressing with

the SHORT_INSTRUCTION bit on the INTERFACE_CONFIG_B

additional information.

DATA PHASE

The data phase immediately follows the instruction phase (as

shown in Figure 63 and Figure 64). The data phase can include

the data for a single-byte register, a multibyte register, or multiple

registers.

If the data phase of a SPI write transaction does not include the

entire byte of data for the register being updated, the contents

of the register are not updated, and the INTERFACE_STATUS_A

MULTIBYTE REGISTERS

Besides the one byte registers, the AD5710R also contains reg-

isters with two bytes of data stored in adjacent addresses that

are referred to as multibyte registers. When writing to a multibyte

this reason, the INTERFACE_CONFIG_C, Bit 5 (STRICT_REGIS-

TER_ACCESS) is read only and set to 1. A write transaction to a

multibyte register takes effect after the 16th SCLK edge of the data

phase.

The address of a multibyte register always depends on the INTER-

FACE_CONFIG_A, Bit 5 (ADDR_ASCENSION). With addresses

descending, the first byte accessed in the data phase must be the

most significant byte of the multibyte register, and each subsequent

byte corresponds to the data in the next lowest address. With

addresses ascending, the first byte accessed in the data phase

must be the least significant byte of the multibyte register, and

each subsequent byte corresponds to the data in the next highest

address.

For example, the DAC_CH0 register is two bytes long, and the

addresses of its least significant byte and most significant byte are

0xD2 and 0xD3, respectively. Figure 65 and Figure 66 show read

transactions of this register for address ascending and descending

mode, respectively.

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