TCC76x
Specification Rev. 0.07
February 23, 2005
32-bit RISC Microprocessor for Digital Media Player
CAMERA INTERFACE
Preliminary
18-9
FIFO States (FIFOSTATE)
0x80000B24
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RE
WE
0
EY
EC1
EC2
FY
FC1
FC2
There are three FIFOs;Y(G) channel, Cb(U/R) channel, Cr(V/B) channel FIFO.
RE [8]
Read Error
0
The empty signal is Low, or empty is High and read enable signal is Low.
1
The empty signal and read enable signal are High.
WE [7]
Read Error
0
The full signal of FIFO is Low, or full is High and write enable signal is Low.
1
The full signal of FIFO and write enable signal are High.
EY [5]
Empty Signal from Y(G) Channel FIFO
0
The state ofY(G) channel FIFO is non-empty.
1
The state of Y(G) channel FIFO is empty.
EC1 [4]
Empty Signal from Cb(U/R) Channel FIFO
0
The state of Cb(U/R) channel FIFO is non-empty.
1
The state of Cb(U/R) channel FIFO is empty.
EC2 [3]
Empty Signal from Cr(V/B) Channel FIFO
0
The state of Cr(V/B) channel FIFO is non-empty.
1
The state of Cr(V/B) channel FIFO is empty.
FY [2]
Full Signal from Y(G) Channel FIFO
0
The state ofY(G) channel FIFO is non-full.
1
The state ofY(G) channel FIFO is full.
FC1 [1]
Full Signal from Cb(U/R) Channel FIFO
0
The state of Cb(U/R) channel FIFO is non-full.
1
The state of Cb(U/R) channel FIFO is full.
FC2 [0]
Full Signal from Cr(V/B) Channel FIFO
0
The state of Cr(V/B) channel FIFO is non-full.
1
The state of Cr(V/B) channel FIFO is full.
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
