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TCC76x
Specification Rev. 0.07
February 23, 2005
32-bit RISC Microprocessor for Digital Media Player
CAMERA INTERFACE
Preliminary
18-8
CMOSIF DMA Configuration Register 1 (CDCR1)
0x80000B14
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
Lock
BS <1:0>
BS [1:0]
Preamble and Status Location
00
The DMAtransfers the image data as 1 word to memory.
01
The DMAtransfers the image data as 2 words to memory.
10
The DMAtransfers the image data as 4 words to memory.
11
The DMAtransfers the image data as 8 words to memory. (default)
Using the burst ofAMBAsystem.
LOCK [2]
Lock Transfer
0
Non-Lock (default)
1
Lock Transfer
CMOSIF DMA Configuration Register 2 (CDCR2)
0x80000B18
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Y-ADDR[31:16]
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Y-ADDR[15:0]
In bypass mode, all data is stored to the base address defined by CDCR2 register. The
other base address registers are ignored.
CMOSIF DMA Configuration Register 3 (CDCR3)
0x80000B1C
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Cb-ADDR[31:16]
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Cb-ADDR[15:0]
CMOSIF DMA Configuration Register 4 (CDCR4)
0x80000B20
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Cr-ADDR[31:16]
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Cr-ADDR[15:0]
FIELD
Description
Y-ADDR [31:0]
Memory BaseAddress forY(G) channel
(Default = 0x20000000)
Cb-ADDR [31:0]
Memory BaseAddress for Cb(U/R) channel (Default = 0x28000000)
Cr-ADDR [31:0]
Memory BaseAddress for Cr(V/B) channel (Default = 0x2C000000)
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