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6V7 Datasheet(PDF) 53 Page - Renesas Technology Corp |
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6V7 Datasheet(HTML) 53 Page - Renesas Technology Corp |
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53 / 298 page  Rev.1.00 May 18, 2004 page 53 of 296 M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP 2.7.5 Interrupt Control Descriptions are given here regarding how to enable or disable maskable interrupts and how to set the priority to be accepted. What is described here does not apply to non-maskable interrupts. Enable or disable a non-maskable interrupt using the interrupt enable flag (I flag), interrupt priority level selection bit, or processor interrupt priority level (IPL). Whether an interrupt request is present or absent is indicated by the interrupt request bit. The interrupt request bit and the interrupt priority level selection bit are located in the interrupt control register of each interrupt. Also, the interrupt enable flag (I flag) and the IPL are located in the flag register (FLG). Figure 2.7.3 shows the interrupt control registers. |
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