6V7 datasheet(76/298 Pages) RENESAS

76 / 298 page

Rev.1.00

May 18, 2004

page 76 of 296

M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP

BCLK

Address

bus

RD signal

WR signal

Data

bus

CPU use

Source

Destination

Dummy

cycle

Dummy

cycle

(1) 8-bit transfers

16-bit transfers from even address and the source address is even.

BCLK

Address

bus

RD signal

WR signal

Data

bus

CPU use

Source

Destination

Dummy

cycle

Dummy

cycle

(3) One wait is inserted into the source read under the conditions in (1)

BCLK

Address

bus

RD signal

WR signal

Data

bus

CPU use

Source

Destination

Dummy

cycle

Dummy

cycle

Source + 1

(2) 16-bit transfers and the source address is odd

Transferring 16-bit data on an 8-bit data bus (In this case, there are also two destination write cycles).

BCLK

Address

bus

RD signal

WR signal

Data

bus

CPU use

Source

Destination

Dummy

cycle

Dummy

cycle

Source + 1

(4) One wait is inserted into the source read under the conditions in (2)

(When 16-bit data is transferred on an 8-bit data bus, there are two destination write cycles).

Note: The same timing changes occur with the respective conditions at the destination as at the source.

Figure 2.9.8 Example of the transfer cycles for a source read

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