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HD404374FT Datasheet(PDF) 107 Page - Renesas Technology Corp |
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HD404374FT Datasheet(HTML) 107 Page - Renesas Technology Corp |
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107 / 161 page  HD404374/HD404384/HD404389/HD404082/HD404084 Series Rev.5.00, Sep.11.2003, page 107 of 161 Bit Read/Write Initial value on reset Bit name 3 R 1 ADRL3 2 R 1 ADRL2 1 — — Not used 0 — —* Not used A/D data register-lower (ADRL: $029) Note: * Should be written with 1 with the emulator. Figure 67 A/D Data Register-Lower (ADRL) Bit Read/Write Initial value on reset Bit name 3 R 1 ADRM3 2 R 1 ADRM2 1 R 1 ADRM1 0 R 1 ADRM0 A/D data register-middle (ADRM: $02A) Figure 68 A/D Data Register-Middle (ADRM) Bit Read/Write Initial value on reset Bit name 3 R 0 ADRU3 2 R 1 ADRU2 1 R 1 ADRU1 0 R 1 ADRU0 A/D data register-upper (ADRU: $02B) Figure 69 A/D Data Register-Upper (ADRU) Module standby register 2 (MSR2: $00E): Writing 1 to bit 1 of module standby register 2 stops the supply of the system clock to the A/D module and cuts the current (I AD) flowing in the ladder resistor. |
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