4518 datasheet(154/160 Pages) RENESAS

154 / 160 page

Rev.3.01

2005.06.15

page 154 of 157

REJ03B0008-0301

4518 Group

BASIC TIMING DIAGRAM

VOLTAGE DROP DETECTION CIRCUIT CHARACTERISTICS

(Ta = –20 °C to 85 °C, unless otherwise noted)

Test conditions

Ta = 25 °C

Mask ROM version

One Time PROM version

Ta = 25 °C

Mask ROM version

One Time PROM version

VDD = 5 V

VDD = 3 V

VDD

→ (VRST– – 0.1 V) (Note 4)

Parameter

Detection voltage

(reset occurs) (Note 1)

Detection voltage

(reset release) (Note 2)

Detection voltage hysteresis

Operation current (Note 3)

Detection time

Symbol

VRST–

VRST+

VRST+–

VRST–

IRST

TRST

Limits

Unit

Min.

3.3

2.7

2.6

3.5

2.9

2.8

Typ.

3.5

3.7

0.2

Max.

3.7

4.2

3.9

4.4

100

1.2

µA

Notes 1: The detected voltage (VRST–) is defined as the voltage when reset occurs when the supply voltage (VDD) is falling.

2: The detected voltage (VRST+) is defined as the voltage when reset is released when the supply voltage (VDD) is rising from reset occurs.

3: When the voltage drop detection circuit is used (VDCE pin = “H”), IRST is added to IDD (power current).

4: The detection time (TRST) is defined as the time until reset occurs when the supply voltage (VDD) is falling to [VRST– – 0.1 V].

STCK

Parameter

Pin (signal) name

Machine cycle

Mi+1

D0–D7

System clock

Port D output

Port D input

Ports P0, P1, P2, P3,

P6 output

Ports P0, P1, P2, P3,

P6 input

D0–D7

INT0, INT1

Interrupt input

P00–P03

P10–P13

P00–P03

P10–P13

P20–P23

P30, P31

P20–P23

P30, P31

P60–P63

4518 Datasheet(PDF) 154 Page - Renesas Technology Corp

4518 Datasheet(HTML) 154 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL