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HD64F36034 Datasheet(PDF) 365 Page - Renesas Technology Corp

Part # HD64F36034
Description  Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Tiny Series
PDF  592 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

HD64F36034 Datasheet(HTML) 365 Page - Renesas Technology Corp

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Section 15 Controller Area Network for Tiny (TinyCAN)
Rev. 4.00 Mar. 15, 2006 Page 333 of 556
REJ09B0026-0400
4. If an arbitrary controller detects an error in a bit of the transmit message, the controller
transmits an error frame. At this time, when the DART or MBn bit in TXCR of the TinyCAN
is set to 1, a transmit request for message 1 is canceled. At the same time, the MBn bits in
TXPR and TXCR are cleared to 0 and the MBn bit in ABACK and the EMPI bit in TCIRR1
are set to 1. The MBn bit in TXACK is always 0.
5. When there is a transmit request at intermission after the error frame, the arbitration for
message 2 is determined and it is transmitted to the CAN bus. When there is no transmit
request, the TinyCAN starts reception.
HRXD
Bus idle
Message 1
[4] Error frame detection
[4] Error frame detection
Transmission for message 1
cannot be cancelled by TXCR
Transmission for message 2
cannot be cancelled by TXCR
Internal arbitration for message 3
can be configurable
[5] Internal arbitration for message 2 is determined
after error frame has ended
[3] Internal arbitration for message 1 is determined
[2] Set MBn
in TXPR
Internal arbitration for message 2 can be configurable
(Transmission settings can be changed by TXPR/TXCR)
Message 1
Message 2
Message 2
Bus idle
SOF
. . . . .
. . . . .
Error flag
Error flag
delimiter
Error flag
delimiter
Intermission
SOF
SOF
Error flag
Intermission
SOF
HTXD
MBn in TXPR
MBn in TXCR
EMPI in TCIRR1
MBn in ABACK
MBn in TXACK
DART
Figure 15.11 Internal Arbitration at Error Detection (MBn in TXCR = 0 and DART = 0)



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