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HD64F36034 Datasheet(PDF) 369 Page - Renesas Technology Corp

Part # HD64F36034
Description  Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Tiny Series
PDF  592 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

HD64F36034 Datasheet(HTML) 369 Page - Renesas Technology Corp

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Section 15 Controller Area Network for Tiny (TinyCAN)
Rev. 4.00 Mar. 15, 2006 Page 337 of 556
REJ09B0026-0400
Receive procedure and operation are as follows.
1. Write data of a receive message to MCn0, MCn4 to MCn7, and MDn0 to MDn7 [n = 0 to 3]
before setting MBCR corresponding to the Mailbox of the receive message to 1 (initial
setting).
2. On detecting EOF of a data frame or remote frame, the TinyCAN compares the receive
message identifier with the identifier set in the receive Mailbox. After LAFM has been read
and then the identifier set in Mailbox 3 (receive mailbox) has been read, the read data is
compared with the receive message identifier. When a mismatch occurs even if the identifier
mask is set, the same comparison procedure is repeated for all other Mailboxes; starting from
Mailbox 2 (receive mailbox) and ending with Mailbox 0. If a mismatch occurs in Mailbox 0,
the TinyCAN clears the temporary buffer and enters the idle state.
3. When the identifier has been compared at the seventh bit of the EOF or the higher bit, the
message is written to the receive Mailbox whose identifier matches that of the receive
message. The identifier, which is masked by LAFM, may be overwritten. If there is more than
one Mailbox whose ID and LAFM matches with those of the receive message, the Mailbox
with the highest number is always to receive the relevant message. Note that Mailboxes with
lower numbers cannot receive that message.
4. After the message has been written to the receive Mailbox, the DFRI bit in TCIRR0 and the
MBn bit in RXPR are set to 1 when the receive message is a data frame, the RFRI bit in
TCIRR0 and the MBn bit in RFPR are set to 1 when the receive message is a remote frame,
and the OVRI bit in TCIRR1 and the MBn bit in UMSR are set to 1 when an overrun or
overwrite occurs.
5. When the MBn bit in RXPR or the MBn bit in RFPR is set to 1, the temporary buffer is
cleared. When the TinyCAN transmits message 2, the internal arbitration is determined, and
the transmit message is transferred to the temporary buffer and output to HTXD after the
temporary buffer has been cleared.



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