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HD64F36034 Datasheet(PDF) 203 Page - Renesas Technology Corp |
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HD64F36034 Datasheet(HTML) 203 Page - Renesas Technology Corp |
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203 / 592 page ![]() Section 12 Timer Z Rev. 4.00 Mar. 15, 2006 Page 171 of 556 REJ09B0026-0400 12.3.2 Timer Mode Register (TMDR) TMDR selects buffer operation settings and synchronized operation. Bit Bit Name Initial Value R/W Description 7 BFD1 0 R/W Buffer Operation D1 0: GRD_1 operates normally 1: GRB_1 and GRD_1 are used together for buffer operation 6 BFC1 0 R/W Buffer Operation C1 0: GRC_1 operates normally 1: GRA_1 and GRD_1 are used together for buffer operation 5 BFD0 0 R/W Buffer Operation D0 0: GRD_0 operates normally 1: GRB_0 and GRD_0 are used together for buffer operation 4 BFC0 0 R/W Buffer Operation C0 0: GRC_0 operates normally 1: GRA_0 and GRC_0 are used together for buffer operation 3 to 1 All 1 Reserved These bits are always read as 1 and cannot be modified. 0 SYNC 0 R/W Timer Synchronization 0: TCNT_1 and TCNT_0 operate as a different timer 1: TCNT_1 and TCNT_0 are synchronized TCNT_1 and TCNT_0 can be pre-set or cleared synchronously |
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