HD64F36034 datasheet(289/592 Pages) RENESAS

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Section 14 Serial Communication Interface 3 (SCI3)

Rev. 4.00 Mar. 15, 2006 Page 257 of 556

REJ09B0026-0400

Bit

Bit Name

Initial

Value

R/W

Description

CKS1

CKS0

R/W

Clock Select 0 and 1

These bits select the clock source for the baud rate

generator.

00:

φ clock (n = 0)

01:

φ/4 clock (n = 1)

10:

φ/14 clock (n = 2)

11:

φ/64 clock (n = 3)

For the relationship between the bit rate register setting

and the baud rate, see section 14.3.8, Bit Rate Register

(BRR). n is the decimal representation of the value of n in

BRR (see section 14.3.8, Bit Rate Register (BRR)).

14.3.6

Serial Control Register 3 (SCR3)

SCR3 is a register that enables or disables SCI3 transfer operations and interrupt requests, and is

also used to select the transfer clock source. For details on interrupt requests, refer to section 14.7,

Interrupts.

Bit

Bit Name

Initial

Value

R/W

Description

TIE

R/W

Transmit Interrupt Enable

When this bit is set to 1, the TXI interrupt request is

enabled.

RIE

R/W

Receive Interrupt Enable

When this bit is set to 1, RXI and ERI interrupt requests

are enabled.

R/W

Transmit Enable

When this bit s set to 1, transmission is enabled.

R/W

Receive Enable

When this bit is set to 1, reception is enabled.

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