HD64F36034 datasheet(290/592 Pages) RENESAS

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Section 14 Serial Communication Interface 3 (SCI3)

Rev. 4.00 Mar. 15, 2006 Page 258 of 556

REJ09B0026-0400

Bit

Bit Name

Initial

Value

R/W

Description

MPIE

R/W

Multiprocessor Interrupt Enable (enabled only when the

MP bit in SMR is 1 in asynchronous mode)

When this bit is set to 1, receive data in which the

multiprocessor bit is 0 is skipped, and setting of the

RDRF, FER, and OER status flags in SSR is disabled.

On receiving data in which the multiprocessor bit is 1, this

bit is automatically cleared and normal reception is

resumed. For details, refer to section 14.6, Multiprocessor

Communication Function.

TEIE

R/W

Transmit End Interrupt Enable

When this bit is set to 1, TEI interrupt request is enabled.

CKE1

CKE0

R/W

Clock Enable 0 and 1

Selects the clock source.

• Asynchronous mode

00: On-chip baud rate generator

01: On-chip baud rate generator

Outputs a clock of the same frequency as the bit rate

from the SCK3 pin.

10: External clock

Inputs a clock with a frequency 14 times the bit rate

from the SCK3 pin.

11:Reserved

• Clocked synchronous mode

00: On-chip clock (SCK3 pin functions as clock output)

01: Reserved

10: External clock (SCK3 pin functions as clock input)

11: Reserved

HD64F36034 Datasheet(PDF) 290 Page - Renesas Technology Corp

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