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HD6433635SW Datasheet(PDF) 126 Page - Renesas Technology Corp |
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HD6433635SW Datasheet(HTML) 126 Page - Renesas Technology Corp |
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126 / 418 page  112 6.3.1 Programming and Verification An efficient, high-speed, high-reliability programming procedure can be used to program and verify data. This procedure programs the chip quickly without subjecting it to voltage stress and without sacrificing data reliability. Data in unused address areas is H'FF. Figure 6.4 shows the basic high-speed, high-reliability programming flow chart. Start Set program/verify mode V = 6.0 V ± 0.25 V, V = 12.5 V ± 0.3 V CC PP Address = 0 n = 0 n + 1 n Program with t = 0.2 ms ±5% → PW Verification OK? Overprogram with t = 0.2n ms OPW Last address? Set read mode V = 5.0 V ± 0.25 V, V = V CC PP CC All addresses read? End Fail n 25 < Address + 1 address → No Yes No Yes Yes No No Yes Figure 6.4 High-Speed, High-Reliability Programming Flow Chart |
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