HD6433635SW datasheet(199/418 Pages) RENESAS

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Table 9.9

Timer G Registers

Name

Abbrev.

R/W

Initial Value

Address

Timer mode register G

TMG

R/W

H'00

H'FFBC

Timer counter G

TCG

—

H'00

—

Input capture register GF

ICRGF

H'00

H'FFBD

Input capture register GR

ICRGR

H'00

H'FFBE

9.4.2

Timer Counter G (TCG)

Bit

76543210

TCG7

TCG6

TCG5

TCG4

TCG3

TCG2

TCG1

TCG0

Initial value

00000000

Read/Write

————————

Timer counter G (TCG) is an 8-bit up-counter which is incremented by an input clock. The input

clock signal is selected by bits CKS1 and CKS0 in timer mode register G (TMG).

To use TCG as an input capture timer, set bit TMIG to 1 in PMR1; to use TCG as an interval

timer, clear bit TMIG to 0.* When TCG is used as an input capture timer, the TCG value can be

cleared at the rising edge, falling edge, or both edges of the input capture signal, depending on

settings in TMG.

When TCG overflows (goes from H'FF to H'00), if the timer overflow interrupt enable bit (OVIE)

is set to 1 in TMG, bit IRRTG in interrupt request register 2 (IRR2) is set to 1. If in addition bit

IENTG in interrupt enable register 2 (IENR2) is set to 1, a CPU interrupt is requested. Details on

interrupts are given in 3.3, Interrupts.

TCG cannot be read or written by the CPU.

Upon reset, TCG is initialized to H'00.

Note: * An input capture signal may be generated when TMIG is rewritten.

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