32186 datasheet(863/1032 Pages) RENESAS

863 / 1032 page

WAIT CONTROLLER

18-21

32185/32186 Group Hardware Manual

Rev.1.10 REJ09B0235-0110 May 15, 07

Figure 18.3.15 Read/Write Timing (for Access with Internal 1 Wait State)

Read

Read (2 cycles)

CLKOUT

A9–A30

CS0#–CS3#

WR#

DB0–DB15

WAIT#

RD#

"H"

Note 1: For details about the Bus Mode Control Register, see Section 17.2.2, "Bus Mode Control Register."

Note 2: For details about the CS Area Wait Control Register, see Section 18.2.1, "CS Area Wait Control Registers."

Notes: • Circles in the above diagram indicate the sampling timing.

• CLKOUT is not output.

(Don't Care)

BHE#, BLE#

Internal

1 wait state

(Don't Care)

Write

Write (2 cycles)

CLKOUT

A9–A30

CS0#–CS3#

WR#

DB0–DB15

WAIT#

RD#

"H"

(Don't Care)

BHE#, BLE#

Internal

1 wait state

(Don't Care)

"H"

Bus Mode Control Register (Note 1)

BUSMOD bit = 1 (byte enable separated)

CS Area Wait Control Register (Note 2)

WAIT bit = 0001 (1 wait)

CWAIT bit = 0 (without CS wait)

SWAIT bit = 0 (without strobe wait)

RECOV bit = 0 (without recovery cycle)

IDLE bit = 0 (without idle cycle)

18.3 Typical Operation of Wait Controller

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