32186 datasheet(967/1032 Pages) RENESAS

967 / 1032 page

ELECTRICAL CHARACTERISTICS

23-51

32185/32186 Group Hardware Manual

Rev.1.10 REJ09B0235-0110 May 15, 07

(11) Read and write timing (2/4)

Symbol

Parameter

Rated Value

Unit

See Figs.

MIN

MAX

23.10.12

23.10.13

tsu(D-RDH)

Data Input Setup Time before Read

[44]

th(RDH-D)

Data Input Hold Time after Read

[45]

tsu(WAITH-RDL)

Data Input Setup Time before Read

tc(CLKOUT) + 21

[132]

tsu(WAITL-RDL)

tw(WAITH)

Wait "H" Pulse Width (Note 1)

[133]

tw(WAITL)

Wait "L" Pulse Width (Note 1)

[134]

tsu(WAITH-BLWL)

[135]

tsu(WAITH-BHWL) Wait Input Setup Time before Write

+ 21

tsu(WAITL-BLWL) (byte write mode)

tsu(WAITL-BHWL)

tw(RDH)

Read "H" Pulse Width

(1+C+S)-5

[55]

tw(RDL)

Read "L" Pulse Width

(1+2W-C-S)-20

[43]

tw(BLWL)

Write "L" Pulse Width

0 wait state:

[51]

tw(BHWL)

(byte write mode)

-11

1-plus wait states:

(2W-C-S)-20

td(RDH-BLWL)

Write Delay Time after Read

tc(CLKOUT)(

+R+ID)-10

[56]

td(RDH-BHWL)

td(BLWH-RDL) Read Delay Time after Write

0 wait state:

[57]

td(BHWH-RDL)

-10

1-plus wait states:

tc(CLKOUT)(1+R+

)-10

td(CSL-RDL)

Chip Select Delay Time before Read

(1+S) -16

[93]

td(CSL-BLWL)

Chip Select Delay Time before Write

(1+S)-16

[95]

td(CSL-BHWL)

td(A-RDL)

Address Delay Time before Read

(1+C+S)-15

[39]

td(CS-RDL)

Chip Select Delay Time before Read

(1+S)-15

[40]

tv(RDH-A)

Address Valid Time after Read

tc(CLKOUT)(R+ID)

[41]

tv(RDH-CS)

Chip Select Valid Time after Read

tc(CLKOUT)

×R

[42]

tpzx(RDH-DZ) Data Output Enable Time after Read

tc(CLKOUT)(

+R+ID)

[46]

td(A-BLWL)

Address Delay Time before Write

(1+C+S)-15

[47]

td(A-BHWL)

(byte write mode)

td(CS-BLWL)

Chip Select Delay Time before Write

(1+S) - 15

[48]

td(CS-BHWL) (byte write mode)

tv(BLWH-A)

Address Valid Time after Write

0 wait state: -5

[49]

tv(BHWH-A)

(byte write mode)

1-plus wait states:

tc(CLKOUT)(

+R)-5

tv(BLWH-CS) Chip Select Valid Time after Write

0 wait state: -5

[50]

tv(BHWH-CS) (byte write mode)

1-plus wait states:

tc(CLKOUT)( +R)-5

td(BLWL-D)

Data Output Delay Time after Write

0 wait state: 5

[52]

td(BHWL-D)

(byte write mode)

1-plus wait states:

15 -

(S+C)

23.10 A.C. Characteristics (when VCCE = 3.3 V)

tc(CLKOUT)

1+C+S

C+S

tc(CLKOUT)

Note 1: Hold a level during tw(WAITH), tw(WAITL) from the position of the minimum value of tsu(WAITH-RDL), tsu(WAITL-

RDL), tsu(WAITH-BLWL), tsu(WAITH-BHWL), tsu(WAITL-BLWL), tsu(WAITL-BHWL).

tc(CLKOUT)

32186 Datasheet(PDF) 967 Page - Renesas Technology Corp

32186 Datasheet(HTML) 967 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL