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3822 Datasheet(PDF) 36 Page - Renesas Technology Corp |
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3822 Datasheet(HTML) 36 Page - Renesas Technology Corp |
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36 / 328 page  1-21 SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS 3822 Group TIMERS The 3822 group has five timers: timer X, timer Y, timer 1, timer 2, and timer 3. Timer X and timer Y are 16-bit timers, and timer 1, timer 2, and timer 3 are 8-bit timers. All timers are down count timers. When the timer reaches “0016”, an underflow occurs at the next count pulse and the correspond- ing timer latch is reloaded into the timer and the count is contin- ued. When a timer underflows, the interrupt request bit corre- sponding to that timer is set to “1”. Read and write operation on 16-bit timer must be performed for both high and low-order bytes. When reading a 16-bit timer, read the high-order byte first. When writing to a 16-bit timer, write the low-order byte first. The 16-bit timer cannot perform the correct op- eration when reading during the write operation, or when writing during the read operation. Fig. 17 Timer block diagram CNTR0 active edge switch bit Timer 1 count source selection bit Real time port control bit “0” “1” P55/CNTR1 “0” f(XIN)/16 (f(XCIN)/16 in low-speed modeV) CNTR1 active edge switch bit “10” Timer Y stop control bit Falling edge detection Period measurement mode Timer Y interrupt request Pulse width HL continuously measurement mode Rising edge detection “00”,“01”,“11” Timer Y operating mode bit Timer X interrupt request Timer X mode register write signal P54/CNTR0 Q Q T S P54 direction register Pulse output mode P54 latch Timer X stop control bit “0” “1” Timer X write control bit Q D Latch Q D Latch “1” “0” “1” “10” Timer X operat- ing mode bit “00”,“01”,“11” f(XIN)/16 (f(XCIN)/16 in low-speed modeV) Pulse width measurement mode CNTR0 active edge switch bit Pulse output mode Q Q T S “0” P56 direction register P56 latch “1” TOUT output active edge switch bit “0” Timer 2 write control bit “0” “1” TOUT output control bit “1” P56/TOUT XCIN Timer 3 count source selection bit “0” “1” Timer 2 interrupt request Timer 3 interrupt request TOUT output control bit Timer 2 count source selection bit Timer 1 interrupt request Data bus f(XIN)/16 (f(XCIN)/16 in low-speed modeV) f(XIN)/16 (f(XCIN)/16 in low-speed modeV) f(XIN)/16(f(XCIN)/16 in low-speed modeV) VInternal clock φ = XCIN/2. CNTR0 interrupt request CNTR1 interrupt request Timer Y operating mode bit “00”,“01”,“10” “11” P60 direction register “0” Real time port control bit “1” P60 P60 latch P61 direction register “0” Real time port control bit “1” P61 P61 latch P60 data for real time port P61 data for real time port Timer Y (low) (8) Timer Y (high) (8) Timer 3 latch (8) Timer 3 (8) Timer 1 latch (8) Timer 1 (8) Timer 2 latch (8) Timer 2 (8) Timer X (low) (8) Timer X (high) (8) Timer X (low) latch (8) Timer X (high) latch (8) Timer Y (low) latch (8) Timer Y (high) latch (8) |
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