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3822 Datasheet(PDF) 86 Page - Renesas Technology Corp |
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3822 Datasheet(HTML) 86 Page - Renesas Technology Corp |
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86 / 328 page ![]() APPLICATION 2.2 Interrupts 2–20 3822 GROUP USER’S MANUAL (2) Interrupt enable bits The interrupt enable bits are allocated to the interrupt control register 1 (address 003E16) and the interrupt control register 2 (address 003F16). The interrupt enable bits control the acceptance of the corresponding interrupt request. When an interrupt enable bit is “0,” the corresponding interrupt request is disabled. If an interrupt request occurs when this bit is “0,” the corresponding interrupt request bit is only set to “1” and this interrupt is not accepted. In this case, unless the interrupt request bit is set to “0” by software, the interrupt request bit remains in the “1” state. When an interrupt enable bit is “1,” the corresponding interrupt is enabled. If an interrupt request occurs when this bit is “1,” this interrupt is accepted (at interrupt disable flag = “0”). Each interrupt enable bit can be set to “0” or “1” by software. (3) Interrupt disable flag The interrupt disable flag is allocated to bit 2 of the processor status register. The interrupt disable flag controls the acceptance of interrupt request. When this flag is “1,” the acceptance of interrupt requests is disabled. When the flag is “0,” the acceptance of interrupt requests is enabled. This flag is set to “1” with the SEI instruction and is set to “0” with the CLI instruction. When a main routine branches to an interrupt processing routine, this flag is automatically set to “1,” so that multiple interrupts are disabled. To use multiple interrupts, set this flag to “0” with the CLI instruction within the interrupt processing routine. Figure 2.2.6 shows an example of multiple inter- rupts. Interrupt enable bit Interrupt sources Interrupt request bit Address Bit Address Bit b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 003E16 003E16 003E16 003E16 003E16 003E16 003E16 003E16 003F16 003F16 003F16 003F16 003F16 003F16 003F16 Table 2.2.2 List of interrupt bits for individual interrupt sources 003C16 003C16 003C16 003C16 003C16 003C16 003C16 003C16 003D16 003D16 003D16 003D16 003D16 003D16 003D16 INT0 INT1 Serial I/O reception Serial I/O transmission Timer X Timer Y Timer 2 Timer 3 CNTR0 CNTR1 Timer 1 INT2 INT3 Key input ADT/A-D conversion |
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