3822 datasheet(89/328 Pages) RENESAS

89 / 328 page

2.2 Interrupts

APPLICATION

2–23

3822 GROUP USER’S MANUAL

(2) Interrupt request register 1 (IREQ1) and interrupt request register 2 (IREQ2)

The interrupt request register 1 (address 003C16) and the interrupt request register 2 (address 003D16)

indicate whether an interrupt request has occurred or not.

Figure 2.2.9 shows the structure of the interrupt request register 1 and Figure 2.2.10 shows the

structure of the interrupt request register 2.

The occurrence of an interrupt request causes the corresponding bit to be set to “1.” This interrupt

request bit is automatically cleared to “0” by the acceptance of the interrupt request.

The interrupt request bits can be set to “0” by software, but it cannot be set to “1” by software.

The occurrence of each interrupt is controlled by the interrupt enable bits (refer to the next item).

Fig. 2.2.9 Structure of interrupt request register 1

b7 b6 b5 b4 b3 b2 b1 b0

Interrupt request register 1 (IREQ1) [Address 3C 16]

Name

Functions

At reset R W

Interrupt request register 1

0 : No interrupt request issued

1 : Interrupt request issued

INT0 interrupt request

bit

INT1 interrupt request

bit

Serial I/O receive

interrupt request bit

Serial I/O transmit

interrupt request bit

: “0” can be set by software, but “1” cannot be set.

Timer X interrupt

request bit

Timer Y interrupt

request bit

Timer 2 interrupt

request bit

Timer 3 interrupt

request bit

0 : No interrupt request issued

1 : Interrupt request issued

0 : No interrupt request issued

1 : Interrupt request issued

0 : No interrupt request issued

1 : Interrupt request issued

0 : No interrupt request issued

1 : Interrupt request issued

0 : No interrupt request issued

1 : Interrupt request issued

0 : No interrupt request issued

1 : Interrupt request issued

0 : No interrupt request issued

1 : Interrupt request issued

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