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3822 Datasheet(PDF) 116 Page - Renesas Technology Corp |
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3822 Datasheet(HTML) 116 Page - Renesas Technology Corp |
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116 / 328 page ![]() APPLICATION 2.3 Timer X and timer Y 3822 GROUP USER’S MANUAL 2–50 2.3.3 Related registers Figure 2.3.10 shows the memory allocation of the timer X- and timer Y-related registers. Each of these registers is described below. Fig. 2.3.10 Memory allocation of timer X- and timer Y-related registers Address Port P5 direction register (P5D) 000B16 002016 Timer X (low-order) (TXL) Timer X mode register (TXM) Timer Y mode register(TYM) Interrupt request register 1 (IREQ1) Interrupt request register 2 (IREQ2) Interrupt control register 1 (ICON1) Interrupt control register 2 (ICON2) 002216 002316 002116 003C16 003D16 003E16 003F16 Timer X (high-order) (TXH) Timer Y (low-order) (TYL) Timer Y (high-order) (TYH) 002716 002816 |
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