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DMA CONTROLLER

13.8 Link array chain transfer mode

13-87

7721 Group User‘s Manual

13.8.3 Operation in link array chain transfer mode

Figure 13.8.6 shows the operation flowchart of the link array chain transfer mode, and Figures 13.8.7 and

13.8.8 show timing diagrams of the link array chain transfer mode (burst transfer mode). In addition, Figure

13.8.9 shows the conditions necessary for timings shown in Figures 13.8.7, 13.8.8, and 13.8.10 through

13.8.14.

For the cycle-steal transfer mode, refer to the following:

• Transfer of transfer parameters in an array state: Figures 13.8.10 and 13.8.11

• All transfers except for that in an array state and except for the last 1-unit transfer of each block: Figure

13.8.12

• Last 1-unit transfer of each block except for the last block: Figure 13.8.13

• Last 1-unit transfer of the last block: Figure 13.8.14

The processing performed in the link array chain transfer mode consists of an array state and a transfer

state.

(1)

Array state

In an array state, transfer parameters are read from the transfer parameter memory in a unit of 2

bytes and transferred to registers SARi, DARi, and TCRi and their latches. As shown in Figure

13.8.2, a transfer parameter consists of 4 bytes (24 bits of data + 8 bits of dummy data).

One bus cycle always consumes 3 cycles of

φ.

_________

During an array state, the DMAACKi pin outputs “H” level.

For the bus request sampling in an array state, refer to section “13.2.1 Bus access control circuit.”

(2)

Transfer state

Data is transferred in a transfer state.

For the bus request sampling in a transfer state, refer to section “13.2.1 Bus access control

circuit.”

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