7721 datasheet(370/577 Pages) RENESAS

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DMA CONTROLLER

13.8 Link array chain transfer mode

13-91

7721 Group User‘s Manual

Figure 13.8.9 shows the conditions necessary for timings shown in Figures 13.8.7, 13.8.8, and 13.8.10

through 13.8.14.

Fig. 13.8.9 Conditions necessary for timings shown in Figures 13.8.7, 13.8.8, and 13.8.10 through

13.8.14

Memory

sa1

da1

tp2

sa2

da2

00000016

tp1

tp1+4

tp1+8

tp1+12

tp2

tp2+4

tp2+8

tp2+12

External data bus width

: 16 bits

Transfer unit

: 16 bits

Transfer method

: 2-bus cycle transfer

Transfer mode

: Burst (“Figure 13.8.7” and “Figure 13.8.8”)

: Cycle-steal (“Figure 13.8.10” through “Figure 13.8.14”)

Transfer source address direction

: Forward

Transfer destination address direction

: Forward

Transfer source Wait

: No

Transfer destination Wait

: No

sa1, sa2, da1, da2

: Transfer parameter (even)

tp1

: Start address of first block’s transfer parameter memory

Transfer block’s number

: 2

Right to use bus

: CPU

→ DMAC → CPU

Memory

First block transfer

First block’s transfer

parameter

sa1

sa1+m–1

sa1+m

sa2+n–1

sa2+n

sa2

Second block’s

transfer parameter

Second block transfer

Memory

da1

da1+m–1

da1+m

da2+n–1

da2+n

da2

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