7721 datasheet(373/577 Pages) RENESAS

373 / 577 page

DMA CONTROLLER

13-94

13.8 Link array chain transfer mode

7721 Group User’s Manual

Fig. 13.8.12 Timing diagram of cycle-steal transfer mode (3)

(sa1+2)L

1, 0 (DMAC)

1-unit transfer

Transition of right

to use bus

Data H

DataL

PCL

PCH

PCL

PCH

(da1+2)L

Data H

DataL

(sa1+2)M

(sa1+2)H

(da1+2)M

(da1+2)H

1, 1 (CPU)

q 1-unit transfer

1-unit transfer is performed with a DMAi request on the following conditions:

• Single transfer mode (except for the last 1-unit transfer)

• Repeat transfer mode (except for the last 1-unit transfer of block)

• Array chain transfer mode (except for the first and last 1-unit transfers of each block)

• Link array chain transfer mode (except for the first and last 1-unit transfers of each block)

ALE

R/W

A0–A7

A8/D8–A15/D15

A16/D0–A23/D7

Bus request sampling

DMAACKi

ST1, ST0

Transition of right

to use bus

q The above figure is the example of the second 1-unit transfer for processing the first block in “Figure 13.8.9.”

q The Bus request caused by DRAM refresh, Hold, or DMA is sampled while the Bus request sampling signal is

“H,” and is accepted.

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