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DMA CONTROLLER

13-98

13.9 DMA transfer time

7721 Group User’s Manual

13.9 DMA transfer time

Calculation of time from the CPU’s relinquishing the right to use bus until its regaining the right under the

following conditions is described with reference to cycles of

φ:

• A DMAi request is generated while the CPU holds the right to use bus.

• The above right is returned to the CPU after completion of DMA transfer for one DMA request.

For the time per 1-unit transfer, refer to section “13.4.1 (2) Bus operation in 2-bus cycle transfer” and

section “13.4.2 (2) Bus operation in 1-bus cycle transfer.”

Also, for the time from DMA request generation until the start of the DMA transfer, refer to section “13.3.4

Processing from DMA request until DMA transfer execution”: and for that from issuing instructions for

forced termination until returning the right to use bus to the CPU, refer to section “13.3.5 (2) Forced

termination.”

13.9.1 Cycle-steal transfer mode

(1)

1-unit transfer

In the following cases, 1-unit transfer is performed at one DMAi transfer. (Refer to “Figure 13.8.12.”)

• Single transfer mode: except for the last 1-unit transfer

• Repeat transfer mode: except for the last 1-unit transfer of a block

• Array chain transfer mode: except for the first and last 1-unit transfers of each block

• Link array chain transfer mode: except for the first and last 1-unit transfers of each block

Right to use

bus

Transfer

CPU

DMAC

CPU

Transition

Fig. 13.9.1 1-unit transfer

Transition of the right to use bus from CPU to DMAC: 1 cycle

DMA transfer per 1-transfer unit:

• In 2-bus cycle transfer···Read cycle + Write cycle

(Add a value which satisfies the read/write conditions. Refer to “Table 13.4.1.”)

• In 1-bus cycle transfer···Refer to “Table 13.4.5.”

Transition of the right to use bus from DMAC to CPU: 1 cycle

[Example]

2-bus cycle transfer, transfer unit =16 bits, external data bus width = 16 bits, and under the following

conditions:

• Transfer source: address direction = forward, start address of data = even, with Wait

• Transfer destination: address direction = backward, start address of data = even, without

Wait

+ + = 1 + (3 + 4) + 1 = 9 cycles

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