7721 datasheet(378/577 Pages) RENESAS

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7721 Group User’s Manual

13-99

DMA CONTROLLER

13.9 DMA transfer time

(2) Last transfer of each block

In the following cases, 1-unit transfer and the processing for 3 cycles are performed sequentially.

(Refer to “Figures 13.8.13 and 13.8.14.”)

• Single transfer mode: the last 1-unit transfer

• Repeat transfer mode: the last 1-unit transfer of a block

• Array chain transfer mode: the last 1-unit transfer of each block (including the last block)

• Link array chain transfer mode: the last 1-unit transfer of each block (including the last block)

Termination

etc.

Right to use

bus

CPU

DMAC

CPU

Transfer

Transition

Fig. 13.9.2 Last transfer of each block

Transition of the right to use bus from CPU to DMAC: 1 cycle

DMA transfer per 1-unit transfer:

• In 2-bus cycle transfer···Read cycle + Write cycle

(Add a value which satisfies the read/write conditions. Refer to “Table 13.4.1.”)

• In 1-bus cycle transfer···Refer to “Table 13.4.5.”

Terminate processing or the last processing of each block: 3 cycles

Transition of the right to use bus from DMAC to CPU: 1 cycle

[Example]

2-bus cycle transfer, transfer unit =16 bits, external data bus width = 16 bits, and under the following

conditions:

• Transfer source: address direction = forward, start address of data = even, with Wait

• Transfer destination: address direction = backward, start address of data = even, without Wait

+ + + = 1 + (3 + 4) + 3 + 1 = 12 cycles

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