7721 datasheet(381/577 Pages) RENESAS

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DMA CONTROLLER

13-102

13.9 DMA transfer time

7721 Group User’s Manual

(2)

Repeat transfer mode

In the repeat transfer mode of burst transfer (edge sense), the method of terminating DMA transfer

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is only the forced termination by the TC input. Therefore, the time from the CPU’s relinquishing the

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right to use bus until regaining the right depends on the timing of the TC input.

Transfer

Right to use

bus

CPU

DMAC

CPU

TC input

1 block

Transfer

Transition

Fig. 13.9.5 Repeat transfer mode (burst transfer mode and edge sense selected)

Transition of the right to use bus from CPU to DMAC: 1 cycle

DMA transfer per 1 block:

• In 2-bus cycle transfer···(Read cycle + Write cycleg1)

× the number of transfersg2

g1: Add a value which satisfies the read/write conditions. Refer to “Table 13.4.1.”

g2: When the transfer unit is 16 bits, the number of transfers = the number of transfer

bytes/2

When the transfer unit is 8 bits, the number of transfers = the number of transfer bytes

• In 1-bus cycle transfer···Refer to “Table 13.4.5.”

Terminate processing: 3 cycles

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DMA transfer of the block at the TC input: above

The number of transfers is assumed to be up to the DMA transfer of 1-unit transfer which was in

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progress at the TC input.

Transition of the right to use bus from DMAC to CPU: 1 cycle

[Example]

External data bus width = 16 bits, 2-bus cycle transfer, transfer unit =16 bits, the number of the

transfer bytes = 10 bytes, and under the following conditions:

• Transfer source: address direction = forward, start address of data = even, with Wait

• Transfer destination: address direction = backward, start address of data = even, without Wait

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• TC is input when the “m”th byte (m = even) of the “n”th block is in transfer.

+ (n – 1) ( + ) + + = 1 + (n – 1){5(3 + 4) + 3} + m/2 + 1 = 38n + m/2 – 36 cycles

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