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7721 Datasheet(PDF) 385 Page - Renesas Technology Corp |
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7721 Datasheet(HTML) 385 Page - Renesas Technology Corp |
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385 / 577 page  14-2 7721 Group User’s Manual DRAM CONTROLLER 14.1 Overview Table 14.1.1 lists the performance specifications of DRAM controller (hereafter called DRAMC). Table 14.1.1 Performance specifications of DRAMC 14.1 Overview, 14.2 Block description Item DRAM area Refreshing method Refresh timer Multiplexed address pins Performance specifications 0 to 15 Mbytes; programmable in a unit of 1 Mbyte ____ ____ CAS before RAS; dispersive refreshing 8 bits 10 14.2 Block description Figure 14.2.1 shows the block diagram of DRAMC. Registers relevant to DRAMC are described below. Bus Access controller RAS and CAS generating circuit Address comparator Address multiplexer Refresh timer 1/(n+1) DRAM control register Address Bits 0–3 A20–A23 A0–A20 f(XIN) 1/16 f16 RAS CAS MA0–MA9 Refresh request Fig. 14.2.1 Block diagram of DRAMC |
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