7721 datasheet(387/577 Pages) RENESAS

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14-4

7721 Group User’s Manual

DRAM CONTROLLER

ST0, ST1

([0,0] is

output.)

ST0, ST1

P106/MA8,

P107/MA9

MA8, MA9

P106, P107

14.2 Block description

(1)

DRAM area select bits (bits 0 to 3)

These 4 bits specify a DRAM area of 15 Mbytes maximum in a unit of 1 Mbyte. Figure 14.2.3 shows

setting examples of DRAM areas.

1 Mbyte

00000016

10000016

80000016

C0000016

FFFFFF16

F0000016

FFFFFF16

4 Mbytes

DRAM area

(00012)

DRAM area

select bits

(Bits 3–0)

(01002)

(10002)

(11112)

Minimum

Maximum

8 Mbytes

15 Mbytes

Fig. 14.2.3 Setting examples of DRAM areas

(2)

DRAM validity bit (bit 7)

When this bit is set to “1,” pin functions for DRAM control become valid, and the refresh timer starts

counting. Table 14.2.1 lists the pin functions for DRAM control.

Table 14.2.1 Pin functions for DRAM control

Pins

A0/MA0

–A7/MA7

MA0–MA7

A0–A7

_______

P104/CAS,

_______

P105/RAS

_______

CAS, RAS

_______

CAS, RAS

_______

CAS, RAS

P104,P105

A16/D0–A23/D7,

A8/D8–A15/D15,

___

_______

R/W, E, BLE, BHE

A16/D0–A23/D7,

A8/D8–A15/D15,

___

_______

________

R/W, E, BLE, BHE

A16/D0–A23/D7,

A8/D8–A15/D15

___

_______

________

R/W, E, BLE, BHE

A16/D0–A23/D7,

A8/D8–A15/D15,

___

_______

________

R/W, E, BLE, BHE

A16/D0–A23/D7,

A8/D8–A15/D15

___

_______

________

R/W, E, BLE, BHE

Operation

DRAM

validity bit

Accessing

DRAM area

DRAM refresh

Other than

the above

—

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