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7721 Datasheet(PDF) 388 Page - Renesas Technology Corp |
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7721 Datasheet(HTML) 388 Page - Renesas Technology Corp |
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388 / 577 page ![]() 14-5 7721 Group User’s Manual DRAM CONTROLLER 14.2 Block description 14.2.2 Refresh timer The refresh timer is an 8-bit timer with a reload register and is used to generate refresh requests for DRAM data. Assuming that the set value of the refresh timer = “n,” the refresh timer counts f16 (n + 1) times. Figure 14.2.4 shows the structure of the refresh timer, and the following formula gives the value to be written to the refresh timer. n = {m [ µs] ! } – 1 n: a set value of the refresh timer (n = 0116–FF16) m: a refresh interval Examples of “m”: an average of 15.625 µs for 512 refresh cycles at 8-ms intervals an average of 125 µs for 512 refresh cycles at 64-ms intervals Fig. 14.2.4 Structure of refresh timer b7 b0 Refresh timer (Address 6616) Functions Bit At reset RW 7 to 0 These bits can be set to “0116” to “FF16.” Assuming that the set value = n, this register divides f16 by (n + 1). Undefined WO Note: Use the LDM or STA instruction for writing to this register. Do not set this register to “0016.” f(XIN) 16 |
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