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7721 Datasheet(PDF) 392 Page - Renesas Technology Corp |
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7721 Datasheet(HTML) 392 Page - Renesas Technology Corp |
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392 / 577 page ![]() 14-9 7721 Group User’s Manual DRAM CONTROLLER 14.4 DRAMC operation Fig. 14.4.1 Waveform example of DRAM control signals Column address E RAS CAS R/W (a) At reading Row address Column address Address Data Read cycle (1 bus cycle) MA0–MA9 A16/D0–A23/D7 A8/D8–A15/D15 E RAS CAS R/W MA0–MA9 A16/D0–A23/D7 A8/D8–A15/D15 (c) At refresh Undefined Refresh cycle Undefined Undefined Floating Transition of right to use bus E RAS CAS R/W MA0–MA9 A16/D0–A23/D7 A8/D8–A15/D15 (b) At writing Row address Address Data Write cycle (1 bus cycle) Undefined Transition of right to use bus |
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