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7721 Datasheet(PDF) 394 Page - Renesas Technology Corp |
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7721 Datasheet(HTML) 394 Page - Renesas Technology Corp |
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394 / 577 page  14-11 7721 Group User’s Manual DRAM CONTROLLER 14.4 DRAMC operation Fig. 14.4.2 Refresh delay time example when CPU is operating E R/W Refresh request Bus request (DRAMC) Bus request sampling ST1,ST0 11 (CPU) 00 (Refresh) Refresh cycle Delay time (Max.): 6.5 cycles of 00 Refresh cycle Transition of right to use bus The following are internal signals: •Refresh request •Bus request (DRAMC) •Bus request sampling Refresh request becomes “0” at an underflow of the refresh timer. Delay time (Min.): 1.5 cycles of Transition of right to use bus Transition of right to use bus Transition of right to use bus 10 (DMAC) 00 (Refresh) Refresh cycle Delay time (Max.): 12.5 cycles of E R/W Refresh request Bus request (DRAMC) Bus request sampling ST1,ST0 The following are internal signals: •Refresh request •Bus request (DRAMC) •Bus request sampling Refresh request becomes “0” at an underflow of the refresh timer. Transition of right to use bus Fig. 14.4.3 Refresh delay time example during DMA transfer |
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