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14-10

7721 Group User’s Manual

DRAM CONTROLLER

DMAC

CPU

14.4.2 Refresh request

When the DRAM validity bit is set to “1,” the refresh timer starts counting down. The count source is

f16.

When the contents of the refresh timer reach “0016,” a refresh request occurs. The refresh timer reloads

the contents of address 6616 and continues counting.

Refresh requests are sampled as bus requests (DRAMC) by using the bus access controller.

As soon as a refresh request is acknowledged by sampling, the following is performed because DRAM

refresh has the highest priority in using the bus.

However, when the CPU or DMAC uses the bus, no bus request is sampled until the CPU or DMAC

releases the bus.

Therefore, in a period from when a refresh request occurs until DRAM refresh is performed, the delay

listed in Table 14.4.1 occurs depending on the refresh request generating timing.

Figures 14.4.2 and 14.4.3 show refresh delay time examples when CPU is operating and during DMA

transfer. For a bus request, refer to “13.2.1 Bus access control circuit.”

When the refresh request is accepted, the right to use the bus is passed to DRAM refresh (1 cycle of

φ). Both of the output levels of ST1 and ST0 are “L.” (The bus status is indicated as [0, 0].)

____

The RAS and the CAS signals are output and the DRAM data is refreshed (refresh cycle: 3 cycles of

φ).

The right to use the bus is passed to the CPU, DRAM or Hold (1 cycle of

φ).

The outputs of ST1 and ST0 change.

Note: In Stop or Wait mode, DRAM refresh is not performed because no refresh request occurs.

Table 14.4.1 Delay time from when refresh request occurs until DRAM refresh is performed

14.4 DRAMC operation

Hold

Maximum (with Wait)

Maximum (no Wait)

Minimum

1.5

4.5

8.5

11.5

6.5

1.5

6.5

12.5

15.5

6.5

1.5

Source of using bus

Array state

Transfer (a unit of 1 transfer)

Transfer (a unit of 1 transfer) + Complete cycle

Delay time (unit:

φ cycle)

Note: The above is applied when Ready is not used. The delay time includes the time for passing the right

to use buses to DRAM refresh (1 cycle).

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