7721 datasheet(390/577 Pages) RENESAS

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14-7

7721 Group User’s Manual

DRAM CONTROLLER

DRAM area setting and DRAM validity selection

DRAM area select bits

b3 b2 b1 b0

•During DRAM area access, CAS, RAS, and MA0–MA9 are output.

•Each time an underflow of the refresh timer occurs, CAS and RAS for refresh are output.

•During refresh, ST0 and ST1 output “L” level.

Division ratio setting for refresh timer

Can be set to “0016” to “FF16” (n).

Refresh timer divides f16 by (n+1).

Refresh timer (Address 6616)

DRAM control register [Address 6416]

0 0 0 0: No DRAM area

0 0 0 1: Addresses F0000016–FFFFFF16 (1 Mbyte)

0 0 1 0: Addresses E0000016–FFFFFF16 (2 Mbytes)

0 0 1 1: Addresses D0000016–FFFFFF16 (3 Mbytes)

0 1 0 0: Addresses C0000016–FFFFFF16 (4 Mbytes)

0 1 0 1: Addresses B0000016–FFFFFF16 (5 Mbytes)

0 1 1 0: Addresses A0000016–FFFFFF16 (6 Mbytes)

0 1 1 1: Addresses 90000016–FFFFFF16 (7 Mbytes)

1 0 0 0: Addresses 80000016–FFFFFF16 (8 Mbytes)

1 0 0 1: Addresses 70000016–FFFFFF16 (9 Mbytes)

1 0 1 0: Addresses 60000016–FFFFFF16 (10 Mbytes)

1 0 1 1: Addresses 50000016–FFFFFF16 (11 Mbytes)

1 1 0 0: Addresses 40000016–FFFFFF16 (12 Mbytes)

1 1 0 1: Addresses 30000016–FFFFFF16 (13 Mbytes)

1 1 1 0: Addresses 20000016–FFFFFF16 (14 Mbytes)

1 1 1 1: Addresses 10000016–FFFFFF16 (15 Mbytes)

DRAM is valid.

(P104–P107 pins function as CAS,RAS, MA8, and MA9.

A0–A7 function as MA0–MA7 when accessing the DRAM

area. Refresh timer starts counting.)

14.3 Setting for DRAMC

Figure 14.3.1 shows an initial setting example for registers relevant to DRAMC.

14.3 Setting for DRAMC

Fig. 14.3.1 Initial setting example for registers relevant to DRAMC

7721 Datasheet(PDF) 390 Page - Renesas Technology Corp