7721 datasheet(391/577 Pages) RENESAS

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14-8

7721 Group User’s Manual

DRAM CONTROLLER

14.4 DRAMC operation

14.4.1 Waveform example of DRAM control signals

Figure 14.4.1 shows a waveform example of the DRAM control signals. When DRAM is accessed, the bus

cycle is always with “wait” (the low-level width of E is equivalent to 2 cycles of

φ). It is not affected by the

wait bit, the wait bit of the transfer source, and the wait bit of the transfer destination.

(1)

Read Cycle

____

In the read cycle, the CAS signal falls with a delay of 0.5 cycle of

φ after the RAS signal has changed

from “H” to “L.” The address bus signal changes from “row address” to “column address” within a

____

period from a fall of RAS until a fall of CAS.

Pins A16/D0–A23/D7 and A8/D8–A15/D15 output addresses and input data in the same way as in reading

external devices other than DRAM.

(2)

Write Cycle

____

In the write cycle, the CAS signal falls with a delay of 1 cycle of

φ after the RAS signal has changed

from “H” to “L.” The address bus signal changes “row address” to “column address” within a period

____

from a fall of RAS until a fall of CAS.

Pins A16/D0–A23/D7 and A8/D8–A15/D15 output addresses and data in the same way as in writing external

devices other than DRAM.

(3)

Refresh Cycle

____

In the refresh cycle, the RAS signal falls with a delay of 0.5 cycle of

φ after the CAS signal has

changed from “H” to “L.”

R/W is undefined.

One refresh request requires 5 cycle of

φ, including the time for passing the right to use buses.

7721 Datasheet(PDF) 391 Page - Renesas Technology Corp