7721 datasheet(389/577 Pages) RENESAS

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14-6

7721 Group User’s Manual

DRAM CONTROLLER

Row address

Column address

Row address

Column address

14.2 Block description

14.2.3 Address comparator

The address comparator examines whether the address to be accessed is within the DRAM area. When

____

this address is within DRAM area, control signals are sent to the RAS and CAS generating circuit and the

address multiplexer.

____

14.2.4 RAS and CAS generating circuit

____

The RAS signal (a timing signal to latch a row address) and the CAS signal (a timing signal to latch a

column address) are generated by a control signal from the address comparator.

14.2.5 Address multiplexer

Address data is time-shared by the control signal from the address comparator and is output to the MA0–

MA9 pins. The time-sharing method depends on the external bus width. Table 14.2.2 lists the time-sharing

method for the address at DRAM access. When the 8-bit external bus width is selected, A0–A19 are time-

shared and are output; when the 16-bit external bus width is selected, A1–A20 are time-shared and are

output.

Table 14.2.2 Time-sharing method for address at DRAM access

Pin name

P107/MA9

A1/MA1 A2/MA2 A3/MA3 A4/MA4 A5/MA5

A7/MA7 P106/MA8

A0/MA0

A10

A11

A12

A13

A14

A15

A16

A17

A18

A17

A18

A19

A20

A19

8-bit external

bus width

16-bit external

bus width

A16

A6/MA6

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